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PanoLogicG2_ReverseEngineering

A repository for a random collection of stuff pertaining to reverse engineering the Pano Logic G2 "zero" client

Introduction

The Pano Logic device was originally a designed as a replacement for a full fat PC based end user device, a class of device known as Thin Client. An article in Hackaday in 2013 (http://hackaday.com/2013/01/11/ask-hackaday-we-might-have-some-fpgas-to-hack/) revealed that these devices basically just consist of a large Xilinx FPGA, plus some peripheral devices (USB, Ethernet, etc). This means they are largely /soft/, feature rich, and eminently hackable and re-purposable.

There are two main Pano Logic devices - the G1, based on a Xilinx Spartan 3 FPGA, and the G2, which uses a Spartan 6. I have concentrated my reverse engineering efforts on the G2, for two main reasons - 1) the S3 is rather long in the tooth now, and 2) the physical construction of the G2 means it is much more hacker friendly (more on this later).

Xilinx Toolchain - Webpack

The version of the Xilinx Webpack that supports all Spartan 6 devices is here: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html or https://bit.ly/2qNIO2N

Documentation is here: https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug1227-spartan6-vm-windows10.pdf or https://bit.ly/2GK4kg2

Interestingly, it is delivered as a Linux VM for Oracle Virtual Box, and only supported on Windows 10. Seems a curious configuration choice, I wonder how difficult it would be to get the VM to run on another virtualisation host? Still, good of Xilinx to release free support for all the S6 devices at last.

G2 Specification

Block Diagram

Block Diagram